Streaming Prefetch

In most commercial processors, data prefetching has been disregarded as a potentially eeective solution to hide cache misses, multi-level caches being widely preferred. However, multi-level caches are mostly eeective at removing capacity and connict misses, while prefetching is particularly eecient for removing compulsory misses, especially in the regular accesses found in numerical codes. One of the main aws of prefetching which stronly limits its popularity in current processors is that it can potentially degrade global cache performance. Wrong address predictions is the rst cause of cache pollution as well as additional memory requests. All existing prefetch schemes are impaired by wrong predictions because they speculate on the next address to be referenced. In this paper, we show that all required informations to avoid the speculative aspect of prefetching can be easily obtained from the compiler, resulting in nearly no wrong predictions. Even when address prediction is awless, prefetching can be hazardous to cache because cache checks (required before sending a prefetch request to limit memory traac) and cache reloads of incoming prefetch requests can result in cache stalls and thus processor stalls, particularly in superscalar processors where the cache can be accessed every cycle. In this paper, we show that addressing these implementation issues can make a prefetching scheme nearly transparent to normal cache operations. We have combined software-assisted address prediction with dedicated hardware support and obtained a prefetching scheme called streaming prefetch where data can ow through the cache nearly without disruption.